// (C) Copyright 2012 Kystar. All rights reserved.

`timescale 1ns/100ps
`default_nettype none

module vin_de_filter 
(
    input  wire          I_pclk,
    input  wire          I_de,
    input  wire [ 23: 0] I_data,
    output reg           O_de,
    output reg  [ 23: 0] O_data,
    input  wire [ 11: 0] I_vin_width
);

/******************************************************************************
                                <localparams>
******************************************************************************/

/******************************************************************************
                              <internal signals>
******************************************************************************/
reg  [ 5: 0] de_dly;
reg  [ 11: 0] o_de_cnt;
reg  [ 23: 0] data_dly0;
reg  [ 23: 0] data_dly1;
reg  [ 23: 0] data_dly2;

/******************************************************************************
                                <module body>
******************************************************************************/
always @(posedge I_pclk)
    begin
    de_dly <= {de_dly[4:0],I_de};
    data_dly0 <= I_data;
    data_dly1 <= data_dly0;
    data_dly2 <= data_dly1;
    end

always @(posedge I_pclk)
    if (O_de)
        begin
        if (o_de_cnt == I_vin_width - 1'b1)
            O_de <= 1'b0;
        end
    else if (de_dly == 6'b000111 && I_de)
        O_de <= 1'b1;

always @(posedge I_pclk)
    if (O_de)
        o_de_cnt <= o_de_cnt + 1'b1;
    else
        o_de_cnt <= 'd0;

always @(posedge I_pclk)
    O_data <= data_dly2;

endmodule
`default_nettype wire

